The present invention relates generally to the field of semiconductor devices, and more particularly to memory devices. Still more particularly, the invention relates to methods for programming semiconductor memory devices by stressing metal oxide semiconductor field effect transistors (MOSFETs) devices to cause hot carrier effect.
Typically, a MOSFET device may be fabricated upon a semiconductor substrate by forming a gate oxide, on top of which a gate electrode resides, and a pair of source/drain electrodes which adjoin the gate oxide and the gate electrode. The method by which a MOSFET device may be fabricated may vary from time to time, as understood by those skilled in the art.
Hot carrier effect is a phenomenon resulting from the injection of charge carriers into gate dielectric layers typically formed of silicon oxide formed beneath gate electrode edges within MOSFET devices. Along with other characteristics, the hot carrier effect within a MOSFET device is manifested by transistor parameters such as sub-threshold current and threshold voltage. In particular, when a MOSFET device is stressed under hot carrier effect, sub-threshold current typically increases while threshold voltage drifts. These drifts in device parameters are caused by the injection of charge carriers from the semiconductor substrate, on top of which a MOSFET device is formed, into the gate oxide of the MOSFET device. Depending on the design parameters of the MOSFET device, the injected charge carriers may generate more interface states within the gate oxide or they may be trapped by mid-gap states of the gate oxide.
Typically, many factors can affect the extent to which hot carrier effect is exhibited in MOSFET devices. These factors include but are not limited to the polarity of the MOSFET device, the hardness of the interface to the injected charge carriers, the trap density within the gate oxide and the potential barrier to charge carrier injection provided by the semiconductor substrate/gate oxide interface. Hot carrier effect can also be enhanced in MOSFET devices where gate dielectric layer thickness as well as channel widths are reduced while operating voltage is maintained. The reduction in gate dielectric layer thickness and channel widths within MOSFET devices at constant operating voltage typically provides an increase in electric field gradients at gate electrode edges within the devices. This increase in electric field gradients allow more charge carriers to be injected into and trapped in the semiconductor substrate and the gate oxide regions beneath gate electrode edges, or the gate dielectric layers.
When charge carriers are fully injected into and trapped in the semiconductor substrate and gate dielectric layers of the MOSFET device, the device is said to be stressed. In a condition wherein hot carrier effect is enhanced and amplified by adjusting the factors mentioned hitherto, electric charge builds up to a point where the semiconductor substrate and gate dielectric layers in the MOSFET device become stressed. As the MOSFET device becomes more stressed, the conductance of the device reduces, thereby exhibiting higher resistance. This resistance remains high until the electrons trapped in the semiconductor substrate and gate dielectric layers in the MOSFET device are removed.
Desirable in the art of semiconductor memory design are additional methods and materials through which one-time programming of non-volatile data can be achieved.